Ion traps have been used to demonstrate all of the components necessary for building a quantum computer or a quantum simulator. Our aim is to show one of the ways to achieve scalability of quantum computer’s components. We are working with silicon-based surface ion traps in cryogenic environment. We collaborate closely with the 2D Arrays and the Nanofiber experiments.
Scalability wish list
Arrays with hundreds or thousands of ion traps can – in principle – be built on a single chip. The aim of this project is to move from “in principle” to “in practice”. There are a number of things which one might want – or need – to do in order to get there:
- arrays of ion traps – in one or, better still, two dimensions. These should be close enough that the ions can be made to interact with each o ther when needed, but also independent enough that the interactions can be turned off
- individual electronic addressing of all necessary electrodes in such a design requires multilayer structures and vias
- the control electronics for such a system could be brought on-chip, which would require integration of, for example, CMOS (Complementary Metal-Oxide-Semiconductors) devices
- individual optical addressing of different ions in the array requires more complex optical systems. This may involve optics outside the vacuum chamber, or even micro-optics in vacuum, at 6 K, built onto the chip.
Creating an array of traps between which the ions can interact requires the trap size to be shrunk considerably. This is not simply “like before, but smaller”: entirely new fabrication methods must be used which, in turn, require entirely new trap geometries.
Rather that the traditional traps fabricated by bulk machining, we use trap geometries in which all electrodes lie on a surface. This allows the traps to be smaller (with the ions a few tens of microns from the electrodes), closer (traps a few scores of microns apart), fabricated more precisely (micron precision), and fabricated more rapidly (days to make, not weeks or months). It also allows for increased complexity of trap design, for only a small overhead in fabrication complexity: multiple trap segments, junctions between different trapping zones, 2D arrays of traps.
Towards scalable ion traps for Quantum Computing
Controlling the quantum state of an ion requires that it is not perturbed by uncontrolled external factors. This includes being hit by any passing atoms, and not being heated by any background fields. Both of these problems can mitigated using a cryostat.
- making large arrays of ions increases the likelihood that one of them will be disturbed by some background gas. To avoid such collisions the trap and surrounding apparatus can be cooled to 6 K. This allows extremely high vacuum (EHV) to be achieved within a day
- making the traps smaller means bringing an ion (~0 K) near to a trap electrode (~300 K). It is possibly not surprising that the closer the ion gets to a hot surface, the faster the ion heats up. (Though establishing exactly what is happening turns out to be non trivial Ion-trap measurements of electric-field noise near surfaces). In any event, making the trap electrodes colder reduces the rate at which the ion is heated.
Beyond that, a cryogenic environment allows new materials to be used, such as silicon. It also means some otherwise not-vacuum-compatible elements can be used (different resistors, capacitors, etc.).
Silicon is a wonderful material, for which a huge toolbox of fabrication techniques have been developed. Unfortunately, it also has very high RF losses, so cannot be simply used as is to make RF ion traps. There are two approaches to using silicon as a trap substrate.
- highly doped (and thereby conducting) silicon is used instead of pure (or “intrinsic”) silicon
- a ground electrode is inserted between the silicon substrate and the trapping electrodes to shield the silicon from the RF fields. We have developed a third possibility Cryogenic silicon surface ion trap
- below 25 K, the charge carriers in intrinsic silicon freeze out, leaving the substrate as a good insulator with low RF losses. This obviates the need for a shielding electrode, which in turn reduces the trap capacitance and the power dissipation, as well as permitting a range of new fabrication techniques
Left: silicon trap design with etched undercuts;
Right: photos of silicon trap, undercuts and trap holder with electronics.
Silicon paterning was done in the Forschungszentrum Mikrotechnik of the Fachhochschule Vorarlberg, with whom we collaborate. Metallization and final treatment of traps was done in our cleanroom.
Work in progress
Our wish list is not yet finished. Here are some of the works in progress:
- we are looking at new ways of implementing vias in our traps (particularly in silicon). This will allow us to create larger, more complex trap designs and still get all of the connections to the outside world
- we have put a resonator for the trap drive, and electronic filters inside the vacuum at 6 K Compact radio-frequency resonator for cryogenic ion traps. Next we are looking to add more complex electronic control, and to integrate electronics onto the chip during the trap fabrication process
- silicon opens up the possibility of optical elements on the chip, such as arrayed waveguides for light delivery, or lenses
- once we have all the pieces in place we will build a fully working, scalable quantum information processor
Kirill Lakhmanskiy (PhD student)
Philip Holz (PhD student)
Regina Lechner (PhD student)
Rainer Blatt (group leader)
Former members: Michael Niedermayr, Michael Brownnutt, Alexander Erhard (now with the LinTrap project), Davide Gandolfi, Adam Pauli
From left to right :
Yves, Ben, Muir, Michael, Kirill, Martin, Philip, Alex, Michi
 "A scalable quantum computer with ions in an array of microtraps", J. I. Cirac and P. Zoller, Nature 404, 579 (2000)
 "Coupled quantized mechanical oscillators", K. R. Brown et al., Nature 471, 196 (2011)
 "Trapped-ion antennae for the transmission of quantum information", M. Harlander et al., Nature 471, 200 (2011)
- "Cryogenic surface ion trap based on intrinsic silicon", M. Niedermayr et al., New J. Phys. 16, 113068 (2014)
- "Ion-trap measurements of electric-field noise near surfaces", M. Brownnutt et al., arXiv:1409.6572
- "Compact radio-frequency resonator for cryogenic ion traps", D. Gandolfi et al., Rev. Sci. Instrum. 83, 084705 (2012)